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A list of all the posts and pages found on the site. For you robots out there, there is an XML version available for digesting as well.
Pages
Posts
portfolio
Project 1 — Full-Custom SRAM
Published:
Full-custom SRAM macro for high-speed ADCs. Process: Samsung 28LPP.
Project 2 — 10-Gbps True Random Number Generator
Published:
All-digital 10-Gbps TRNG using an ML-resistant middle square method. Process: TSMC 28HPC+.
Project 3 — 2.5-GS/s Pipelined SAR ADC
Published:
2.5-GS/s pipelined SAR ADC. Process: TSMC 28HPC+.
Project 4 — 40-GS/s 32-Channel Time-Interleaved SAR ADC
Published:
40-GS/s, 32-channel time-interleaved SAR ADC for PAM-4 SerDes Rx. Process: TSMC 28HPC+.
publications
Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique
Published in Journal of Semiconductor Technology and Science (JSTS), 2021
A time-interleaved noise-shaping SAR ADC based on a CIFF architecture with a redundancy error correction technique.
Recommended citation: Kihyun Kim, Jihyun Baek, Jong Hyun Kim, and Hyungil Chae. (2021). "Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique." Journal of Semiconductor Technology and Science (JSTS).
An IF Reconfigurable Bandpass Noise-Shaping SAR ADC for IoT and Mobile Application
Published in Electronics Letters (EL), 2022
An intermediate-frequency reconfigurable bandpass noise-shaping SAR ADC targeting IoT and mobile applications.
Recommended citation: Jong Hyun Kim, et al. (2022). "An IF Reconfigurable Bandpass Noise-Shaping SAR ADC for IoT and Mobile Application." Electronics Letters (EL). doi:10.1049/ell2.12947
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A 7-Bit 4-GS/s Quad-Channel Time-Interleaved SAR ADC With 2-Then-1-Bit Cycle Conversion
Published in IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022
A 7-bit 4-GS/s quad-channel time-interleaved SAR ADC with 2-then-1-bit cycle conversion.
Recommended citation: Jihyun Baek, Jong Hyun Kim, Gyuchan Cho, Jintae Kim, and Hyungil Chae. (2022). "A 7-Bit 4-GS/s Quad-Channel Time-Interleaved SAR ADC With 2-Then-1-Bit Cycle Conversion." Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC).
A 10-Gbps, 0.121-pJ/bit, All-Digital True Random-Number Generator Using Middle Square Method
Published in IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022
A 10-Gbps, 0.121-pJ/bit, all-digital true random-number generator using the middle square method.
Recommended citation: Jong Hyun Kim and Hyungil Chae. (2022). "A 10-Gbps, 0.121-pJ/bit, All-Digital True Random-Number Generator Using Middle Square Method." Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC).
A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method
Published in IEEE Journal of Solid-State Circuits (JSSC), 2024
A 10-Gb/s true random number generator using a machine-learning-resistant middle square method.
Recommended citation: Jong Hyun Kim, et al. (2024). "A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method." IEEE Journal of Solid-State Circuits (JSSC). doi:10.1109/JSSC.2023.3346428
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A Multispectral Vision Sensor with Embedded Convolutional Neural Network using Programmable Fractional Weights and nMOS-Only PWM Pixels
Published in IEEE Symposium on VLSI Circuits, Kyoto, Japan, 2025
A multispectral vision sensor with an embedded convolutional neural network using programmable fractional weights and nMOS-only PWM pixels.
Recommended citation: Hyoungjun Kim, Jong Hyun Kim, et al. (2025). "A Multispectral Vision Sensor with Embedded Convolutional Neural Network using Programmable Fractional Weights and nMOS-Only PWM Pixels." IEEE Symposium on VLSI Circuits, Kyoto, Japan.
talks
Technical Tutorial: Machine Learning-Based SerDes Equalizer Design
Published:
Invited technical tutorial at the IEEE Workshop on Microelectronics and Electron Devices (WMED) on machine learning-based equalizer design for high-speed SerDes interfaces.